A clock recovery circuit is required for regenerating a digital signal after it has propagated through a distorting and noisy medium.
When a digital signal has been subjected to filtering or to various kinds of distortion, and has been degraded with noise, it can be processed in real time in order to regenerate it substantially perfectly. Over a long distance, digital transmission may require regeneration to take place many times.
Regeneration is made possible by the fact that even though the signal may be degraded by rounding and noise, use can be made of a priori information about the signal structure. This structure includes:
a clock rate at frequency fr, which determines charateristic instants at which discrete states should appear; and
a predetermined number of such discrete states, e.g. two.
When performing regeneration, noise and distortion give rise to errors. Such errors are undetectable a priori unless a bit-by-bit comparison can be made with the initial signal.
In the simplest case of a purely binary signal, regeneration can be performed as follows:
being by making a decision concerning the level of the received signal, i.e. by interpreting whether it represents a binary 0 or a binary 1. This operation is very similar to clipping a signal that exceeds predetermined thresholds; and
then recover the clock in order to perform sampling under the best possible conditions. Ideally, the recovered clock should have no interfering fluctuations relative to the initial clock. This implies that a spectrum line fr=1/T can be used, whereas this particular spectrum line is normally absent from digital signals.
One might be tempted to create such a spectrum line by a local oscillator set to the nominal value of fr, however this technique is unusable because of the fundamental impossibility of obtaining two sinusoidal signals in two different locations having rigorously identical frequency and phase. This is because:
oscillators cannot be set to any frequency with sufficient accuracy; and
frequency and phase are continually being disturbed by phenomena such as temperature and noise.
This explains why, when receiving a carrier modulated by a digital technique, it is necessary to have a circuit for recovering the clock which is used for regeneration purposes from the received signal itself.
The requirements for such a clock recovery circuit include the following points:
(a) immunity to distortion, and in particular to multi-path propagation distortion;
(b) low residual jitter in the absence of distortion;
(c) satisfactory admissible jitter, i.e. a large amount of jitter should not lead to transmission errors; and
(d) phase locking to obtain an eye diagram which is as open as possible.
The object of the present invention is to provide a clock recovery circuit which satisfies the above requirements in an advantageous manner.